This invention relates to memory address checking in computer systems.
Computer systems typically include mechanisms for ensuring the correctness of data, for example through the use of parity and error correction codes. Such mechanisms are often applied to the data paths between processing elements, I/O elements and main memory. Indeed, it is common for parity or error correction codes to be stored along with data in main memory. As a result of this the parity or error correction codes are available to check the validity of data when subsequently read from memory. Accordingly, it is possible for the validity and correctness of data to be verified at all stages along the data path from the processing elements to memory and back again.
It is also known to employ parity or error correction codes for ensuring the correctness of addresses on an address bus. However, the protection provided by the use of such codes for checking addresses effectively stops at the entry to the memory subsystem, such that address errors within the memory subsystem can go undetected.
Accordingly, an aim of the present invention is to improve the degree of security of memory operation in a computer system.